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First Principles / Part V · The frontier & the industry / Chapter 28

First Principles · The frontier & the industry · 28

The compute supply chain

Behind every GPU is a chain that runs from a Dutch lithography machine to a Taiwanese fab to a power substation — and nearly every link is held by one to three companies. It's the most concentrated supply chain in modern industry, and the tightest link sets the pace of the whole build-out.

Read at your depth:  01 The answer · 02 Intuition · 03 Mechanics · 04 The math · 05 The code · 06 The economics · 07 Sources

01The answer, then the intuition

A chain of near-monopolies

A finished AI accelerator passes through a startling gauntlet, and at almost every stage there is effectively one supplier the world depends on. The extreme-ultraviolet lithography machines that print the smallest features? One company, ASML. The fabrication of leading-edge chips? Overwhelmingly one, TSMC. The AI GPUs themselves? Overwhelmingly one, Nvidia. The high-bandwidth memory? Three makers. The advanced packaging that stitches it together? Capacity-constrained at a handful.

Because it's a chain, its output is set by the tightest link — not the average. Click through the stages; the highlighted one is the current bottleneck that caps how many chips the whole industry can actually ship:

Sand to a running model — the chokepoint chain

Illustrative relative capacity per stage; the red stage is the binding constraint. Click any node.

02Mechanics

The links, in order

  • EUV lithography → ASML. The machines that pattern the finest chip features use extreme-ultraviolet light. ASML is the sole maker on Earth; without it, the leading edge stops. A single point of failure at the very top of the stack.
  • Leading-edge fabrication → TSMC. Turning designs into wafers at the smallest nodes is dominated by TSMC, concentrated in Taiwan — the geopolitical fault line the whole industry watches.
  • GPU design → Nvidia. Nvidia designs the accelerators and, crucially, the CUDA software ecosystem that locks developers in. It captures enormous margin because it sells the one part everyone needs.
  • HBM & packaging → a few makers. High-bandwidth memory (SK Hynix, Samsung, Micron) and advanced packaging (CoWoS) are the frequent real bottlenecks — you can design the chip, but not get enough memory stacked onto it.
  • Assembly & power → hyperscalers and the grid. The chips become clusters inside data centers, and the final, growing constraint is electrical: gigawatts of power, gated by turbines, transmission, and permits.

Each link is both a pricing-power point — a near-monopoly that captures margin — and a fragility point, where one disruption ripples through everything downstream. Concentration is efficient and lucrative right up until it isn't.

04The math

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The law of the minimum

A serial supply chain obeys Liebig's law of the minimum: total throughput is the capacity of its smallest stage, not the sum or the average:

$$ \text{output} = \min_{i}\; \text{capacity}_i $$

Adding capacity anywhere except the binding stage does nothing — a fact that makes bottleneck identification the entire game. And because each stage is a near-monopoly, its reliability $r_i$ is a single point of failure; the chain's reliability is the product:

$$ R_{\text{chain}} = \prod_{i} r_i $$

With many stages each held by one supplier, even high individual reliability multiplies down — six stages at 98% each give $0.98^{6} \approx 0.89$. Concentration raises margins at every link and lowers the reliability of the whole. The build-out can only proceed as fast as its scarcest input allows, which is why a shortage in one unglamorous component — memory, packaging, a transformer for the substation — can throttle the entire industry.

05The code

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Finding the binding link

The chain's real output is its minimum stage — and which stage that is, is where all the leverage lives.

bottleneck.py

stages = {   # illustrative annual capacity, GPU-equivalent units
    "EUV litho (ASML)":        6.0, "Leading-edge fab (TSMC)": 5.0,
    "GPU design (Nvidia)":     5.5, "HBM (3 makers)":          3.5,
    "CoWoS packaging":         3.8, "Data-center power":       4.0,
}
cap = min(stages.values())
binding = next(n for n, v in stages.items() if v == cap)
print(f"chain output capped at {cap} by: {binding}")
# chain output capped at 3.5 by: HBM (3 makers)
# -> adding fab or litho capacity changes nothing; only more HBM raises output

06The economics

Where the margin — and the fragility — lives

The chain → money

This is the physical supply side of the Circuit, and it explains where the money pools. Each chokepoint is a near-monopoly, so each captures outsized margin — Nvidia's, TSMC's, and ASML's economics are what a single-supplier link looks like on an income statement. When a stage is the binding constraint, its owner has extraordinary pricing power; the shortages are the profits.

They're also the fragility. A serial chain of near-monopolies means one disrupted link — an HBM shortage, a packaging constraint, a grid it can't power, or a shock to Taiwan — throttles everything downstream. The build-out's pace isn't set by ambition or capital; it's set by the tightest link, whatever it happens to be this quarter.

For a research desk, tracking the chain is how you separate a genuine acceleration from a temporary squeeze. When one link loosens, output jumps; when another tightens, it stalls — regardless of demand. Reading the bottleneck is reading the real speed limit of AI, and it's exactly the kind of ground-truth signal the Circuit is built to watch.

07Going deeper

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The primary sources

SemiAnalysis · deep coverage of HBM, CoWoS packaging, and accelerator supply.
ASML — EUV lithography · the sole supplier of leading-edge lithography.
IEA — Electricity & data-center demand · power as the emerging constraint.
CSIS — Mapping the Semiconductor Supply Chain · concentration and geographic risk.

Cite this chapter: Divergent Compute, "The compute supply chain", First Principles, 2026. divergentcompute.com/first-principles-supply-chain · v1.0 · CC-BY.

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